The present invention is directed to a method and apparatus for determining phase changes of a reference input signal of a phase-locked loop.
Network clock reference signals are required at switching centers and network nodes in synchronous, digital communication networks. Especially high demands are made of reference frequencies with respect to stability for reliable transmission of data. In the prior art the required long-term stability can only be guaranteed with cesium atomic frequency normals.
For reasons of economic feasibility, clock generators synchronized by a national frequency normal are employed in digital communication networks. In what are referred to as slave equipment, the clock signal is recovered from the transmitted signals by synchronization of the clock generator. The desired, phase-locked coupling of the clock signals in the synchronous system, however, can be negatively influenced by this type of clock generating. Given the phase-locked loops (PLL) usually employed, the basic principle applies that the coupling between input signal and output clock signal becomes more rigid at higher limit frequencies. On the other hand, the regenerator equipped with the PLL circuit must switch into what is referred to as memory mode and itself supply an optimally frequency-exact clock signal given outage of the synchronizing signal, for example due to a disturbed transmission link. The stability of this clock, however, increases for lower limit frequency of the phase-locked loop. For this reason, clock generators having different limit frequencies are employed for synchronization. In order for a regenerator to switch into memory mode in which it supplies a stable clock, it is first necessary to determine and check the constancy of the incoming signal. Given fast and relatively large frequency changes, a phase difference can be determined by comparing the input signal to the regenerated output signal at constant time intervals and the frequency deviation can be in turn determined from this phase difference. Frequency deviations greater than approximately 10.sup.-7 can be recognized on the basis of these methods. The determination of smaller frequency deviations becomes more difficult when the necessary observation times must be selected longer. In these cases, the output clock signal in the PLL control circuit follows the input signal and can no longer be considered fixed.
One possibility for determining small phase or, respectively, frequency changes is to employ separate, highly constant reference oscillators that are independent of a reference signal. What is disadvantageous about this proposal are the additional costs for an oscillator that provides the required constant frequency.